]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: Parametrize VLV_DDL registers
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 26 Jun 2014 14:02:37 +0000 (17:02 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 8 Aug 2014 15:43:54 +0000 (17:43 +0200)
commitb90fd0b106a541c505c3a8c3c01609302413a579
tree54c23bd54915b13dfb31749e5101cd5f1adfb31a
parentc4ccb103ec4609e3590236fe6438add59b91f393
drm/i915: Parametrize VLV_DDL registers

The VLV/CHV DDL registers are uniform, and neatly enough the register
offsets are sane so we can easily unify them to a single set of defines
and just pass the pipe as the parameter to compute the register offset.

Note that we now fill out the drain latency for pipe C on CHV which we
didn't do before. The rest of the pipe C watermarks are still untouched
but that will be remedied later by adding a proper cherryview_update_wm()
function.

v2: Add a note about CHV pipe C changes (Paulo)

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c