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(parent: ca95d81) | patch
drm/i915: DSPFW and BLC regs are in the display offset range
authorJesse Barnes <jbarnes@virtuousgeek.org>
Fri, 8 Mar 2013 18:45:59 +0000 (10:45 -0800)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Sat, 23 Mar 2013 11:18:01 +0000 (12:18 +0100)
commitb889af9b196c350a2e435f943c9f75759bf7b830
tree7f1ea27b82e81cdb5e3c0031104cd6966ab0ac5atree | snapshot
parentca95d81f08fe9869b6375270acc363e9d48e5f40commit | diff
drm/i915: DSPFW and BLC regs are in the display offset range

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
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