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(parent: 299fdd0) | patch
drm/nouveau/disp/sor/gf119: both links use the same training register
authorBen Skeggs <bskeggs@redhat.com>
Fri, 3 Jun 2016 04:37:40 +0000 (14:37 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Mon, 6 Jun 2016 22:11:14 +0000 (08:11 +1000)
commitb436a4d5d052614654bc62c3768890b0ba1428a7
tree210fe44ee38c2cfcd0741f444e94288dffdb6709tree | snapshot
parent299fdd015c30b85873373f68d84628a602ee4d56commit | diff
drm/nouveau/disp/sor/gf119: both links use the same training register

It appears that, for whatever reason, both link A and B use the same
register to control the training pattern.  It's a little odd, as the
GPUs before this (Tesla/Fermi1) have per-link registers, as do newer
GPUs (Maxwell).

Fixes the third DP output on NVS 510 (GK107).

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c diff | blob | history
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