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(parent: 1bd7f7c) | patch
drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid
authorRohit Khaire <rohit.khaire@amd.com>
Fri, 4 Jun 2021 15:02:56 +0000 (11:02 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 8 Jun 2021 18:03:55 +0000 (14:03 -0400)
commitb33f6b62ff3f42433d01eac0a5d2521b587cbc51
tree20df74a67b30a58b93d950f2bce2b4e4c67e69a4tree | snapshot
parent1bd7f7caa683a0643bbf038cefc23c9fcbd52c2ecommit | diff
drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid

RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different
offsets for Sienna Cichlid

Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c diff | blob | history
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