]> git.baikalelectronics.ru Git - kernel.git/commit
drm/bridge: ti-sn65dsi86: Fix output polarity setting bug
authorQiqi Zhang <eddy.zhang@rock-chips.com>
Fri, 25 Nov 2022 10:45:58 +0000 (18:45 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 14 Dec 2022 10:30:44 +0000 (11:30 +0100)
commitaf2622d49acc0c43fd2c76b0271354a18e8c1e52
tree139892b613ddf87f98ddf24213d0a932bb22195e
parentf97ff565555666a6ff95348ec105b70dca5c9259
drm/bridge: ti-sn65dsi86: Fix output polarity setting bug

[ Upstream commit 8c115864501fc09932cdfec53d9ec1cde82b4a28 ]

According to the description in ti-sn65dsi86's datasheet:

CHA_HSYNC_POLARITY:
0 = Active High Pulse. Synchronization signal is high for the sync
pulse width. (default)
1 = Active Low Pulse. Synchronization signal is low for the sync
pulse width.

CHA_VSYNC_POLARITY:
0 = Active High Pulse. Synchronization signal is high for the sync
pulse width. (Default)
1 = Active Low Pulse. Synchronization signal is low for the sync
pulse width.

We should only set these bits when the polarity is negative.

Fixes: 75a27075bea1 ("drm/bridge: add support for sn65dsi86 bridge driver")
Signed-off-by: Qiqi Zhang <eddy.zhang@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20221125104558.84616-1-eddy.zhang@rock-chips.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/gpu/drm/bridge/ti-sn65dsi86.c