]> git.baikalelectronics.ru Git - kernel.git/commit
ASoC: Intel: Skylake: fix reset controller sequencing
authorJayachandran B <jayachandran.b@intel.com>
Fri, 18 Dec 2015 09:42:03 +0000 (15:12 +0530)
committerMark Brown <broonie@kernel.org>
Sun, 10 Jan 2016 12:19:01 +0000 (12:19 +0000)
commitaedad4f3281c285dc1443a06897b1f43d20b7f81
tree89295d33fcb50b73dba25302a9979fb013cf9cd0
parentcd2a181de5ac9350786e7035104bbf16d7a804ac
ASoC: Intel: Skylake: fix reset controller sequencing

MISCBDCGE is a new register for Misc Backbone clock gate control
which is useful to control while resetting the link and ensuring
controller is in required state so add API to control it

HW recommends that we reset with CGCTL.MISCBDCGE disabled, so add
that while doing init chip and reset sequence.

Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/intel/skylake/skl-sst-ipc.h
sound/soc/intel/skylake/skl.c
sound/soc/intel/skylake/skl.h