]> git.baikalelectronics.ru Git - kernel.git/commit
MIPS: Honor L2 bypass bit
authorKevin Cernekee <cernekee@gmail.com>
Thu, 21 Oct 2010 03:05:42 +0000 (20:05 -0700)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 29 Oct 2010 18:08:52 +0000 (19:08 +0100)
commitae04f35f4e764bb8c3ac0afa691ef5c67210dc84
treeb9a39c79e7080b9790936618a704439d057cb78a
parent54d98264e4a139dbda5a9dbdd8676a7085353ba3
MIPS: Honor L2 bypass bit

On many of the newer MIPS32 cores, CP0 CONFIG2 bit 12 (L2B) indicates
that the L2 cache is disabled and therefore Linux should not attempt
to use it.

[Ralf: Moved the code added by Kevin's original patch into a separate
function that can easily be replaced for platforms that need more a
different probe.]

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: linux-mips@linux-mips.org>
Cc: <linux-kernel@vger.kernel.org>
Patchwork: https://patchwork.linux-mips.org/patch/1723/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mm/sc-mips.c