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csky: Fixup barrier design
authorGuo Ren <guoren@linux.alibaba.com>
Sun, 20 Dec 2020 03:39:27 +0000 (03:39 +0000)
committerGuo Ren <guoren@linux.alibaba.com>
Tue, 12 Jan 2021 01:52:40 +0000 (09:52 +0800)
commitabf7ed9b168a41ee7c33f9d5d74baf8692efee2a
tree5aa937f17bd6579d02cb046c34f812b1e41e5a18tree | snapshot
parentb70ebb0d1cb079356583f9c7482f8b32238c8197commit | diff
csky: Fixup barrier design

Remove shareable bit for ordering barrier, just keep ordering
in current hart is enough for SMP. Using three continuous
sync.is as PTW barrier to prevent speculative PTW in 860
microarchitecture.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
arch/csky/include/asm/barrier.h diff | blob | history
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