]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: Save latest known sink CRC to compensate delayed counter reset.
authorRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 23 Jul 2015 23:35:49 +0000 (16:35 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 14 Aug 2015 16:16:28 +0000 (18:16 +0200)
commitab965dfb9551f928f3258f1a1c012aec5c3ad792
treedc1c9ca8be43eed145d26acec94435381d2b22ab
parente61201fb44e9a19a97a1dd169d42aa4078fd526e
drm/i915: Save latest known sink CRC to compensate delayed counter reset.

By Vesa DP 1.2 Spec TEST_CRC_COUNT should be
"reset to 0 when TEST_SINK bit 0 = 0."

However for some strange reason when PSR is enabled in
certain platforms this is not true. At least not immediatelly.

So we face cases like this:

first get_sink_crc operation:
     count: 0, crc: 000000000000
     count: 1, crc: c101c101c101
returned expected crc: c101c101c101

secont get_sink_crc operation:
     count: 1, crc: c101c101c101
     count: 0, crc: 000000000000
     count: 1, crc: 0000c1010000
should return expected crc: 0000c1010000

But also the reset to 0 should be faster resulting into:

get_sink_crc operation:
     count: 1, crc: c101c101c101
     count: 1, crc: 0000c1010000
should return expected crc: 0000c1010000

So in order to know that the second one is valid one
we need to compare the pair (count, crc) with latest (count, crc).

If the pair changed you have your valid CRC.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_drv.h