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(parent: dd4a0ac) | patch
drm/tegra: dpaux: Fix transfers larger than 4 bytes
authorThierry Reding <treding@nvidia.com>
Thu, 11 Jun 2015 16:33:48 +0000 (18:33 +0200)
committerThierry Reding <treding@nvidia.com>
Fri, 12 Jun 2015 14:22:46 +0000 (16:22 +0200)
commita9924955d3ed623789ae37e2a404aabe2e6bf223
treec71bc338728059b18bfd0f031956fbb73e288751tree | snapshot
parentdd4a0ac5a66093ba1477238fa2d0e835dd935ff6commit | diff
drm/tegra: dpaux: Fix transfers larger than 4 bytes

The DPAUX read/write FIFO registers aren't sequential in the register
space, causing transfers larger than 4 bytes to cause accesses to non-
existing FIFO registers.

Fixes: 11f1be8af9f1 ("drm/tegra: Add eDP support")
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/dpaux.c diff | blob | history
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