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(parent: 071ee47) | patch
arm: zynq: Label whole PL part as fpga_full region
authorMichal Simek <michal.simek@xilinx.com>
Tue, 14 Feb 2017 16:40:21 +0000 (17:40 +0100)
committerMichal Simek <michal.simek@xilinx.com>
Wed, 2 Aug 2017 07:11:51 +0000 (09:11 +0200)
commita929ea0cdd6921cf4874687277ac7031f2ae842f
treef43f64b13e373fef33bf6558be02171fb27c31e8tree | snapshot
parent071ee47079d620c817b209b133717e67c8ec1d50commit | diff
arm: zynq: Label whole PL part as fpga_full region

This will simplify dt overlay structure for the whole PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
arch/arm/dts/zynq-7000.dtsi diff | blob | history
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