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(parent: f7a3f1b) | patch
drm/amdgpu/swsmu/smu12: fix force clock handling for mclk
authorAlex Deucher <alexander.deucher@amd.com>
Mon, 28 Sep 2020 18:16:25 +0000 (14:16 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 29 Sep 2020 21:09:59 +0000 (17:09 -0400)
commita914faa331cf9520534faf27d10bb4870879f604
treedeae39a868d0aa6cb06bbb325534eae2617ab495tree | snapshot
parentf7a3f1bc2c13d4840176abc199ff5ce459c9fbf3commit | diff
drm/amdgpu/swsmu/smu12: fix force clock handling for mclk

The state array is in the reverse order compared to other asics
(high to low rather than low to high).

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1313
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/renoir_ppt.c diff | blob | history
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