]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 26 Apr 2016 16:46:32 +0000 (19:46 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 28 Apr 2016 15:11:06 +0000 (18:11 +0300)
commita80453a36a117e96f37e358a660eca25201549f8
tree72b8642a44c9a443379e5b0b58a44d35468e50c0
parentccefeac778b1437e6ddd4846fa97fa3138cb5e5c
drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency

Update CDCLK_FREQ on BDW after changing the cdclk frequency. Not sure
if this is a late addition to the spec, or if I simply overlooked this
step when writing the original code.

This is what Bspec has to say about CDCLK_FREQ:
"Program this field to the CD clock frequency minus one. This is used to
 generate a divided down clock for miscellaneous timers in display."

And the "Broadwell Sequences for Changing CD Clock Frequency" section
clarifies this further:
"For CD clock 337.5 MHz, program 337 decimal.
 For CD clock 450 MHz, program 449 decimal.
 For CD clock 540 MHz, program 539 decimal.
 For CD clock 675 MHz, program 674 decimal."

Cc: stable@vger.kernel.org
Cc: Mika Kahola <mika.kahola@intel.com>
Fixes: a10777f29d22 ("drm/i915: BDW clock change support")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461689194-6079-2-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c