]> git.baikalelectronics.ru Git - kernel.git/commit
MIPS: BMIPS: Add special cache handling in c-r4k.c
authorKevin Cernekee <cernekee@gmail.com>
Tue, 21 Oct 2014 04:28:00 +0000 (21:28 -0700)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 24 Nov 2014 06:45:12 +0000 (07:45 +0100)
commita698996fd39aa54bd59057fc7e474fe361f1750e
treeaca830adb2572cf37c1060c1b0ce4f9ac78700c0
parent791caca2a4b4004c3ebda75c1613ca98a0a2108c
MIPS: BMIPS: Add special cache handling in c-r4k.c

BMIPS435x and BMIPS438x have a single shared L1 D$ and load/store unit,
so it isn't necessary to raise IPIs to keep both CPUs coherent.

BMIPS5000 has VIPT L1 caches that handle aliases in hardware, and its I$
fills from D$.  But a special sequence with 2 SYNCs and 32 NOPs is needed
to ensure coherency.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8165/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mm/c-r4k.c