ARM: 8682/1: V7M: Set cacheid iff DminLine or IminLine is nonzero

ARM: 8682/1: V7M: Set cacheid iff DminLine or IminLine is nonzero

Cache support is optional feature in M-class cores, thus DminLine or
IminLine of Cache Type Register is zero if caches are not implemented,
but we check the whole CTR which has other features encoded there.
Let's be more precise and check for DminLine and IminLine of CTR
before we set cacheid.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>