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(parent: 389f417) | patch
net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES
authorJisheng Zhang <jszhang@marvell.com>
Wed, 30 Mar 2016 11:55:21 +0000 (19:55 +0800)
committerDavid S. Miller <davem@davemloft.net>
Thu, 31 Mar 2016 19:15:01 +0000 (15:15 -0400)
commita36df262f44cfa697491803b52f9158d6e8ea861
treed276b0b55aaeb9ca6efbefc74c79e0f3fb4f5882tree | snapshot
parent389f417f5dfbddc347e159f25eefaf5ea78ffdbdcommit | diff
net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES

The mvneta is also used in some Marvell berlin family SoCs which may
have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE
usage with L1_CACHE_BYTES.

And since dma_alloc_coherent() is always cacheline size aligned, so
remove the align checks.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/marvell/mvneta.c diff | blob | history
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