]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915/bdw: Support BDW caching
authorBen Widawsky <benjamin.widawsky@intel.com>
Tue, 5 Nov 2013 03:56:49 +0000 (19:56 -0800)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 8 Nov 2013 17:09:45 +0000 (18:09 +0100)
commita2ba8a559601dc49797945fc36aa9a87cf3c94a7
tree0f2f77866f71fb65d8ac1295f035454aef2621ba
parentff9259009a6de61e78c3fd993bffcce533b862cc
drm/i915/bdw: Support BDW caching

BDW caching works differently than the previous generations. Instead of
having bits in the PTE which directly control how the page is cached,
the 3 PTE bits PWT PCD and PAT provide an index into a PAT defined by
register 0x40e0. This style of caching is functionally equivalent to how
it works on HSW and before.

v2: Tiny bikeshed as discussed on internal irc.

v3: Squash in patch from Ville to mirror the x86 PAT setup more like
in arch/x86/mm/pat.c. Primarily, the 0th index will be WB, and not
uncached.

v4: Comment for reason to not use a 64b write on the PPAT.

v5: Add a FIXME comment that the caching bits in the PAT registers
might be wrong due to doc confusion.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_gem_gtt.c
drivers/gpu/drm/i915/i915_reg.h