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(parent: 04f59c4) | patch
feat(intel): fix bridge disable and reset
authorAng Tien Sung <tien.sung.ang@intel.com>
Mon, 13 Mar 2023 01:32:40 +0000 (09:32 +0800)
committerSieu Mun Tang <sieu.mun.tang@intel.com>
Mon, 10 Apr 2023 16:17:00 +0000 (00:17 +0800)
commit9ce82519c65f0dd93d2673ebb967d02f52b19a04
tree11527690b64f5bc69481f339c30114a8dec64041tree | snapshot
parent04f59c4a642b35699498dde40b3b0a98440e98e4commit | diff
feat(intel): fix bridge disable and reset

Fix bridge sideband manager register clear and set incorrect
implementation. To support non-graceful full bridge disable
and enable.

Signed-off-by: Ang Tien Sung <tien.sung.ang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I651f3ec163d954e8efb0542ec33bce96e51992db
plat/intel/soc/common/include/socfpga_f2sdram_manager.h diff | blob | history
plat/intel/soc/common/soc/socfpga_reset_manager.c diff | blob | history
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