]> git.baikalelectronics.ru Git - kernel.git/commit
clk: imx: pll14xx: avoid glitch when set rate
authorPeng Fan <peng.fan@nxp.com>
Mon, 9 Sep 2019 03:39:34 +0000 (03:39 +0000)
committerStephen Boyd <sboyd@kernel.org>
Wed, 18 Sep 2019 05:53:34 +0000 (22:53 -0700)
commit9c37deac4ea2153ee9176c94f69228b9425b095e
tree89446415db3fa7640019dc1d218fd004574ba3c2
parent61a173691121824d34131d068eea38b829effeca
clk: imx: pll14xx: avoid glitch when set rate

According to PLL1443XA and PLL1416X spec,
"When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
output unstable clock until lock time passes. PLL1416X/PLL1443XA may
generate a glitch at FOUT."

So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
In the end of set rate, BYPASS will be cleared.

When prepare clock, also need to take care to avoid glitch. So
we also follow Spec to set BYPASS before RESETB changed from 0 to 1.
And add a check if the RESETB is already 0, directly return 0;

Fixes: 7b05f9ea0569 ("clk: imx: Add PLLs driver for imx8mm soc")
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-2-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/imx/clk-pll14xx.c