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(parent: 201b2c3) | patch
CLK: HSDK: CGU: add support for 148.5MHz clock
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Wed, 11 Mar 2020 13:41:15 +0000 (16:41 +0300)
committerStephen Boyd <sboyd@kernel.org>
Fri, 29 May 2020 04:06:39 +0000 (21:06 -0700)
commit9c265172e0e9ba5cc8c633414a8d88ca332b6336
tree6c89a056b78a8189ce5d9518978d096a691c1853tree | snapshot
parent201b2c35968e5a6a35247c476c81729f6d1c213ccommit | diff
CLK: HSDK: CGU: add support for 148.5MHz clock

Add support for 148.5MHz clock for HDMI PLL

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Link: https://lkml.kernel.org/r/20200311134115.13257-4-Eugeniy.Paltsev@synopsys.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/clk-hsdk-pll.c diff | blob | history
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