]> git.baikalelectronics.ru Git - kernel.git/commit
drm/amd/display: Disconnect pipe separetely when disable pipe split
authorAlvin Lee <alvin.lee2@amd.com>
Thu, 30 Jul 2020 03:08:59 +0000 (23:08 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 10 Aug 2020 21:26:52 +0000 (17:26 -0400)
commit9bbd3d1b2f45d9f9b3cd5feed812774059e3ca7a
tree083215b488e703bb422147213714bca8f7a87a65
parent7c7a0e8adde7ffe87deffe54613e5c8d1b66b2a8
drm/amd/display: Disconnect pipe separetely when disable pipe split

[Why]
When changing pixel formats for HDR (e.g. ARGB -> FP16)
there are configurations that change from 2 pipes to 1 pipe.
In these cases, it seems that disconnecting MPCC and doing
a surface update at the same time(after unlocking) causes
some registers to be updated slightly faster than others
after unlocking (e.g. if the pixel format is updated to FP16
before the new surface address is programmed, we get
corruption on the screen because the pixel formats aren't
matching). We separate disconnecting MPCC from the rest
of  the  pipe programming sequence to prevent this.

[How]
Move MPCC disconnect into separate operation than the
rest of the pipe programming.

Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h