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(parent: e6c9598) | patch
clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handling
authorMarek Vasut <marek.vasut+renesas@gmail.com>
Tue, 27 Apr 2021 17:36:39 +0000 (19:36 +0200)
committerMarek Vasut <marek.vasut+renesas@gmail.com>
Fri, 21 May 2021 13:00:17 +0000 (15:00 +0200)
commit94629d60855ba6263d4590459671f94c452190f4
tree518a679d6fd290cf789b696b278efa593bcccd41tree | snapshot
parente6c9598f2fe77caac00f78c4224da9f258612530commit | diff
clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handling

Most of the PLLx, MAIN, FIXED clock handlers are calling very similar
code, which determines parent rate and then applies multiplication and
division. The only difference is whether multiplication is fixed factor
or coming from CRx register. Deduplicate the code into a single function.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
drivers/clk/renesas/clk-rcar-gen3.c diff | blob | history
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