]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: Request full SSEU enablement on Gen9
authorJeff McGee <jeff.mcgee@intel.com>
Fri, 13 Feb 2015 16:27:56 +0000 (10:27 -0600)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 23 Feb 2015 22:57:13 +0000 (23:57 +0100)
commit8f71da8feeb0400f5032e2e4735711a647ad2903
treec5b4330d9050c0385e4fdfa7704e45a1a4520eec
parent3726f6f47feb4099bee8e1c1f8c730e61749146b
drm/i915: Request full SSEU enablement on Gen9

On Gen9 the render power gating can leave slice/subslice/EU in
a partially enabled state. We must make an explicit request for
full SSEU enablement through the Render Power Clock State
register when resuming render work. This register is save/
restored in the logical ring context image for execlist
submission mode. Initialize its value in each LRC image to
request full enablement according to the device SSEU config.

Thanks to Sharma Ankitprasad and Akash Goel for highlighting the
issue and proposing the initial fix on which this patch is based.

v2: Adjusted the names of the power gating support flags to fit
    update of an earlier patch.

Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Reviewed-by: "Akash Goel <akash.goel@intel.com>"
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_lrc.c