]> git.baikalelectronics.ru Git - kernel.git/commit
drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_mode_set()
authorLiu Ying <victor.liu@nxp.com>
Tue, 19 Apr 2022 01:08:48 +0000 (09:08 +0800)
committerGuido Günther <agx@sigxcpu.org>
Fri, 6 May 2022 07:55:16 +0000 (09:55 +0200)
commit8e9c3dc53e3fe36c8aaf0452cc7d2db557c3faac
tree614437ac7bba1c4f6fa049d350c5769289156384
parent8c557069680d24824dfacaa8f344867bbe011c8e
drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_mode_set()

The Northwest Logic MIPI DSI host controller embedded in i.MX8qxp
works with a Mixel MIPI DPHY + LVDS PHY combo to support either
a MIPI DSI display or a LVDS display.  So, this patch calls
phy_set_mode() from nwl_dsi_mode_set() to set PHY mode to MIPI DPHY
explicitly.

Cc: Guido Günther <agx@sigxcpu.org>
Cc: Robert Chiras <robert.chiras@nxp.com>
Cc: Martin Kepplinger <martin.kepplinger@puri.sm>
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: NXP Linux Team <linux-imx@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Acked-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Guido Günther <agx@sigxcpu.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220419010852.452169-2-victor.liu@nxp.com
drivers/gpu/drm/bridge/nwl-dsi.c