]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page
authorMichel Thierry <michel.thierry@intel.com>
Mon, 11 Jan 2016 11:39:27 +0000 (11:39 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 12 Jan 2016 21:15:54 +0000 (22:15 +0100)
commit8af48a94242ae497887d8dffef674f3de66057d7
tree00198a8f5c3223ddb480194a53e8bbc86ca78fc7
parent4eb0e6e69563a783aad023140c39ce11028a7a7d
drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page

Kernel and userspace are able to handle 4GB (1<<32) address space range,
but "A32 Stateless Model" is not. According to documentation, A32 accesses
are based on General State Base Address and bound checking is in place.
Because size field (instruction State Base Address) limitation, it is not
possible to address full 4GB memory region.

A32 Stateless Model is used by some libraries and without this patch, the
last page of 4GB address space is not accessible in 32bit processes.

Reported-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1452512367-23614-1-git-send-email-michel.thierry@intel.com
Cc: drm-intel-fixes@lists.freedesktop.org
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_gem.c