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(parent: 1f46a3f) | patch
drm/i915/icl: Define TA_TIMING_PARAM registers
authorMadhav Chauhan <madhav.chauhan@intel.com>
Sun, 16 Sep 2018 10:53:30 +0000 (16:23 +0530)
committerJani Nikula <jani.nikula@intel.com>
Wed, 26 Sep 2018 13:01:52 +0000 (16:01 +0300)
commit8934475d889f38f9014605ae8c7c544c5d2ebee1
tree2f9625f5b060f915ae83b304cdc67914837ff487tree | snapshot
parent1f46a3f14aef6458a595cdadf207b68521ca6977commit | diff
drm/i915/icl: Define TA_TIMING_PARAM registers

This patch defines DSI_TA_TIMING_PARAM and
DPHY_TA_TIMING_PARAM registers used in
dphy programming.

v2: Changes (Jani N)
    - Define mask/shift for bitfields
    - Use bitfields name as per BSPEC
    - Define remaining bitfields

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1537095223-5184-8-git-send-email-madhav.chauhan@intel.com
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
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