]> git.baikalelectronics.ru Git - kernel.git/commit
x86: c_p_a() fix: reorder TLB / cache flushes to follow Intel recommendation
authorAndi Kleen <ak@suse.de>
Wed, 30 Jan 2008 12:33:52 +0000 (13:33 +0100)
committerIngo Molnar <mingo@elte.hu>
Wed, 30 Jan 2008 12:33:52 +0000 (13:33 +0100)
commit86772be8ba82a7e6d72e936215c37fd6df3d4cb5
treeb40ef3575608c40243cef41965ee16f807a7da7c
parent70e595dfebcb6fcad7e7efadc0ee5e886a76d43a
x86: c_p_a() fix: reorder TLB / cache flushes to follow Intel recommendation

Intel recommends to first flush the TLBs and then the caches
on caching attribute changes. c_p_a() previously did it the
other way round. Reorder that.

The procedure is still not fully compliant to the Intel documentation
because Intel recommends a all CPU synchronization step between
the TLB flushes and the cache flushes.

However on all new Intel CPUs this is now meaningless anyways
because they support Self-Snoop and can skip the cache flush
step anyway.

[ mingo@elte.hu: decoupled from clflush and ported it to x86.git ]

Signed-off-by: Andi Kleen <ak@suse.de>
Acked-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
arch/x86/mm/pageattr_32.c
arch/x86/mm/pageattr_64.c