mips: mt76xx: Flush d-cache in arch_misc_init() to solve d-cache issues

mips: mt76xx: Flush d-cache in arch_misc_init() to solve d-cache issues

It has been noticed, that sometimes the d-cache is not in a
"clean-state" when U-Boot is running on MT7688. This was detected when
using the ethernet driver (which uses d-cache) and a TFTP command does
not complete. Flushing the complete d-cache (again?) here seems to fix
this issue.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>