]> git.baikalelectronics.ru Git - kernel.git/commit
staging: fsl-dpaa2/eth: Change RX buffer alignment
authorBogdan Purcareata <bogdan.purcareata@nxp.com>
Sun, 29 Oct 2017 08:20:42 +0000 (08:20 +0000)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 3 Nov 2017 15:19:27 +0000 (16:19 +0100)
commit8338d44a1c4d5a7115eb3824b289e901fce64803
treef14593151626a3f7c03982139933f2b813522332
parent792a9de73fffd0c7fff55eeb7f489c1363d18e60
staging: fsl-dpaa2/eth: Change RX buffer alignment

The WRIOP hardware block v1.0.0 (found on LS2080A board)
requires data in RX buffers to be aligned to 256B, but
newer revisions (e.g. on LS2088A, LS1088A) only require
64B alignment.

Check WRIOP version and decide at runtime which alignment
requirement to configure for ingress buffers.

Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c
drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h