]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: Enable DP panel power sequencing for ValleyView
authorShobhit Kumar <shobhit.kumar@intel.com>
Fri, 15 Jun 2012 18:55:14 +0000 (11:55 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 20 Jun 2012 12:51:38 +0000 (14:51 +0200)
commit8294bf792c6f4697ca174f475e57076384b7a2ed
tree32411014028f4b63854ededa441e7a81a8f5c733
parentaab21fabbcc7c9b3079b70e85c65d524d9ca4893
drm/i915: Enable DP panel power sequencing for ValleyView

VLV supports two dp panels, there are two set of panel power sequence
registers which needed to be programmed based on the configured
pipe. This patch add supports for the same

Acked-by: Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Beeresh G <beeresh.g@intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Drop the lone hunk and only keep the register definitions - I
loathe incomplete bandaids. Also add a comment that this is for vlv.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h