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(parent: aee2f33) | patch
feat(ti): set L2 cache ECC and and parity on A72 cores
authorAndrew Davis <afd@ti.com>
Tue, 10 Jan 2023 19:25:42 +0000 (13:25 -0600)
committerAndrew Davis <afd@ti.com>
Fri, 13 Jan 2023 00:42:57 +0000 (18:42 -0600)
commit81858a353f8e45f5cc57ce855188043b1745ea08
treeb7ff1786b13c6dac4bc1e84c1542d6dca192f7dctree | snapshot
parentaee2f33a675891f660fc0d06e739ce85f3472075commit | diff
feat(ti): set L2 cache ECC and and parity on A72 cores

The Cortex-A72 based cores on K3 platforms have cache ECC and
parity protection, enable these.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Icd00bc4aa9c1c48f0fb2a10ea66e75e0b146ef3c
include/lib/cpus/aarch32/cortex_a72.h diff | blob | history
include/lib/cpus/aarch64/cortex_a72.h diff | blob | history
plat/ti/k3/common/k3_helpers.S diff | blob | history
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