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(parent: 9881bb9) | patch
fix(intel): mailbox store QSPI ref clk in scratch reg
authorJit Loon Lim <jit.loon.lim@intel.com>
Fri, 19 Aug 2022 11:40:17 +0000 (13:40 +0200)
committerSieu Mun Tang <sieu.mun.tang@intel.com>
Tue, 22 Nov 2022 15:56:42 +0000 (23:56 +0800)
commit7f9e9e4b40152c0cb52bcc53ac3d32fd1c978416
tree336bdf156e3d1dd1ff2682c0e89d5f5de0a26b1atree | snapshot
parent9881bb93a3bc0a3ea37e9f093e09ab4b360a9e48commit | diff
fix(intel): mailbox store QSPI ref clk in scratch reg

When HPS requests QSPI controller access the SDM returns the QSPI
reference clock frequency. Store the provided reference clock frequency
(in kHz) in BOOT_SCRATCH_COLD_0 register (bits [27:0]) as u-boot
QSPI driver expects this.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6b95c19db602387a79ff10abdebbc57abb0c07ff
plat/intel/soc/common/include/socfpga_system_manager.h diff | blob | history
plat/intel/soc/common/soc/socfpga_mailbox.c diff | blob | history
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