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(parent: 5171a30) | patch
clk: tegra: Fix cclk_lp divisor register
authorMichał Mirosław <mirq-linux@rere.qmqm.pl>
Tue, 19 Sep 2017 02:48:10 +0000 (04:48 +0200)
committerThierry Reding <treding@nvidia.com>
Wed, 1 Nov 2017 14:00:06 +0000 (15:00 +0100)
commit7f39374e35cc40452a84087d82851c05cc08383f
treeefc64cd2a02c839a6fb1a657da81ab76ec7cfdf2tree | snapshot
parent5171a30e99bc0c632584273bbf9173fd8a6b01f6commit | diff
clk: tegra: Fix cclk_lp divisor register

According to comments in code and common sense, cclk_lp uses its
own divisor, not cclk_g's.

Fixes: 8031d5266b66 ("clk: tegra: add clock support for Tegra30")
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra30.c diff | blob | history
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