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clk: sunxi: Allwinner A20 output clock support
authorChen-Yu Tsai <wens@csie.org>
Tue, 24 Dec 2013 13:26:17 +0000 (21:26 +0800)
committerEmilio López <emilio@elopez.com.ar>
Sat, 28 Dec 2013 20:14:21 +0000 (17:14 -0300)
commit7cd8bd0fd456c7d0e72f8db39dfd6b9a69a4587b
treeec7de73187cf68dd890e8e62dcab535e4434e052tree | snapshot
parentaa5c0baf0714f075a251a200a88ef87e76241ddbcommit | diff
clk: sunxi: Allwinner A20 output clock support

This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to "module 0"
type clocks, with different offsets and widths for clock factors.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
Documentation/devicetree/bindings/clock/sunxi.txt diff | blob | history
drivers/clk/sunxi/clk-sunxi.c diff | blob | history
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