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(parent: 72efdd9) | patch
drm/msm/dpu: Fix VBIF_XINL_QOS_LVL_REMAP_000 register offset
authorAngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Tue, 12 Jan 2021 19:26:26 +0000 (20:26 +0100)
committerRob Clark <robdclark@chromium.org>
Sun, 31 Jan 2021 19:34:35 +0000 (11:34 -0800)
commit79a3d67c71f3ec87b681e64ee1a9c81f24f363f1
treea04b21401739c8cc55f65c1935274e04993c8c54tree | snapshot
parent72efdd90c7a6dcdc13a98d32f93191caa7e9d3c8commit | diff
drm/msm/dpu: Fix VBIF_XINL_QOS_LVL_REMAP_000 register offset

On DPUs prior to version 4 the VBIF_XINL_QOS_LVL_REMAP_000 register
is at 0x570 offset from vbif base instead of 0x590, due to the
VBIF_XINL_QOS_RP_REMAP_000 having less instances (less possible XINs).

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c diff | blob | history
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