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(parent: 27e21fc) | patch
clk: zynq: Update the parameters to zynq_clk_register_periph_clk
authorShubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Tue, 22 Feb 2022 13:09:03 +0000 (18:39 +0530)
committerStephen Boyd <sboyd@kernel.org>
Tue, 29 Mar 2022 17:17:49 +0000 (10:17 -0700)
commit76a3dcba1e881c69e7c7cdd9d6f585600eb3b2ab
tree9e4ac23aa71109930d0a79d3475f72064b0bea65tree | snapshot
parent27e21fccd1bd4c0fbd307ce6abe231c379a05db6commit | diff
clk: zynq: Update the parameters to zynq_clk_register_periph_clk

In case there are only one gate or the two_gate is 0 the clk1 clock
passed is not used. We are passing 0 which is arm_pll.
Pass a invalid clock instead.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20220222130903.17235-3-shubhrajyoti.datta@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/zynq/clkc.c diff | blob | history
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