]> git.baikalelectronics.ru Git - kernel.git/commit
powerpc/dts/fsl: t2080rdb: reorder the Cortina PHY XFI lanes
authorCamelia Groza <camelia.groza@nxp.com>
Thu, 20 Sep 2018 11:47:01 +0000 (14:47 +0300)
committerScott Wood <oss@buserror.net>
Sat, 20 Oct 2018 23:23:56 +0000 (18:23 -0500)
commit70225c7f53070eea1255753588d64b2a965a3f1d
tree90544b9ecadb7956583dda6650d6cf4f486aabee
parent424452be6b3d8ead4d142defa1a7439fba0a40a3
powerpc/dts/fsl: t2080rdb: reorder the Cortina PHY XFI lanes

According to the T2080RDB schematics, for the CS4315 PHY, the XFI 1 lane is
connected to SFP 2 and the XFI 2 lane is connected to SFP 1. Change the
device tree to reflect the correct PHY order and port association.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Scott Wood <oss@buserror.net>
arch/powerpc/boot/dts/fsl/t2080rdb.dts