]> git.baikalelectronics.ru Git - kernel.git/commit
e1000e: Increase PHY PLL clock gate timing
authorRaanan Avargil <raanan.avargil@intel.com>
Tue, 22 Dec 2015 13:35:02 +0000 (15:35 +0200)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Wed, 24 Feb 2016 22:44:01 +0000 (14:44 -0800)
commit6cfe8bee433179ffcc773857026a8d04e7b90000
treeecc3fea1a86ee7434af79efb8c1400ec5083143b
parent5fad8d4e05eb3e3d31f715624fd2bd3f22aac400
e1000e: Increase PHY PLL clock gate timing

Several packet loss issues were reported for which the root cause for
them was an incorrect configuration of internal HW PHY clock gating
mechanism by SW.
This patch provides the correct mechanism.

Signed-off-by: Raanan Avargil <raanan.avargil@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/e1000e/ich8lan.c
drivers/net/ethernet/intel/e1000e/ich8lan.h