]> git.baikalelectronics.ru Git - kernel.git/commit
MIPS: Loongson: Invalidate special TLBs when needed
authorHuacai Chen <chenhc@lemote.com>
Thu, 3 Mar 2016 01:45:11 +0000 (09:45 +0800)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 13 May 2016 12:02:14 +0000 (14:02 +0200)
commit6cbd12a75b090cfb127b712bad5c9aa707a382bc
treed23c5f9cf1b096b3bc67f458a6b0984b664d7cbf
parent98695e6a88af4c87155e510a447720954a3a00ab
MIPS: Loongson: Invalidate special TLBs when needed

Loongson-2 has a 4 entry itlb which is a subset of jtlb, Loongson-3 has
a 4 entry itlb and a 4 entry dtlb which are subsets of jtlb. We should
write diag register to invalidate itlb/dtlb when flushing jtlb because
itlb/dtlb are not totally transparent to software.

For Loongson-3A R2 (and newer), we should invalidate ITLB, DTLB, VTLB
and FTLB before we enable/disable FTLB.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12753/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mipsregs.h
arch/mips/kernel/cpu-probe.c
arch/mips/mm/tlb-r4k.c