]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: Revert workaround for disabling L3 cache aging on BYT
authorSinclair Yeh <sinclair.yeh@intel.com>
Wed, 19 Feb 2014 21:09:31 +0000 (13:09 -0800)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 5 Mar 2014 20:30:01 +0000 (21:30 +0100)
commit6cb708ee7822375af92c6ec4d6b253bb53378ae2
tree5399d45f013259df85c367061b9d05c3c7c98ab1
parentaaca2582807ab3fa1c8f8586ed3b9cedfcb7aed0
drm/i915: Revert workaround for disabling L3 cache aging on BYT

V2:  edit the commit message to contain more info
The W/A spreadsheet says this is still required, but the b-spec says
it's not for BYT-T.  So the documentation is not clear.  However,
our experience with the other SKUs of BYT-I/M on Android and Linux
suggests that setting this bit actually causes GPU hang for certain
OGL benchmark applications.

Removing this bit completely resolves the GPU hangs.

Signed-off-by: Sinclair Yeh <sinclair.yeh@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c