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| author | Alexandre Belloni <alexandre.belloni@bootlin.com> | |
| Thu, 22 Mar 2018 15:15:23 +0000 (16:15 +0100) | ||
| committer | Marc Zyngier <marc.zyngier@arm.com> | |
| Thu, 22 Mar 2018 15:52:27 +0000 (15:52 +0000) | ||
| commit | 6a655ceb8e17056e1a8c7460777bc668df761ad8 | |
| tree | 99e3b3e6c902e22fb1dbee21b982ed9c2d533bc2 | tree | snapshot |
| parent | 7f6d4b465e2c723dae30608d1511eb3afc2fe044 | commit | diff |
| Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt | [new file with mode: 0644] | blob |