]> git.baikalelectronics.ru Git - kernel.git/commit
RISC-V: Fix compilation without RISCV_ISA_ZICBOM
authorAndrew Jones <ajones@ventanamicro.com>
Fri, 21 Oct 2022 06:22:39 +0000 (11:52 +0530)
committerAnup Patel <anup@brainfault.org>
Fri, 21 Oct 2022 06:22:39 +0000 (11:52 +0530)
commit69a467dd3d6226f2fe84bbe78ec97836a71ec330
tree67f55881cfc0ed09d8ea7e25165ec850022a2694
parent6358759813eb1920a7e9bc57799a80a94f6c66b8
RISC-V: Fix compilation without RISCV_ISA_ZICBOM

riscv_cbom_block_size and riscv_init_cbom_blocksize() should always
be available and riscv_init_cbom_blocksize() should always be
invoked, even when compiling without RISCV_ISA_ZICBOM enabled. This
is because disabling RISCV_ISA_ZICBOM means "don't use zicbom
instructions in the kernel" not "pretend there isn't zicbom, even
when there is". When zicbom is available, whether the kernel enables
its use with RISCV_ISA_ZICBOM or not, KVM will offer it to guests.
Ensure we can build KVM and that the block size is initialized even
when compiling without RISCV_ISA_ZICBOM.

Fixes: 3978d3b49987 ("RISC-V: Clean up the Zicbom block size probing")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/cacheflush.h
arch/riscv/mm/cacheflush.c
arch/riscv/mm/dma-noncoherent.c