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(parent: 552af31) | patch
qed: Configure cacheline size in HW
authorTomer Tayar <Tomer.Tayar@cavium.com>
Thu, 6 Apr 2017 12:58:30 +0000 (15:58 +0300)
committerDavid S. Miller <davem@davemloft.net>
Thu, 6 Apr 2017 21:26:31 +0000 (14:26 -0700)
commit68d26a7f979c5f5411bf0dd1ad832301cff99dab
tree01739ed7b696f08f2d03d388030516b1e55e22edtree | snapshot
parent552af313590e6d4f47981601da511fb1f832fca5commit | diff
qed: Configure cacheline size in HW

Default HW configuration is optimal for an architecture where cache
line size is 64B.

During chip initialization, properly initialize the cache line size
in HW to avoid possible redundant PCI transactions.

Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/qlogic/qed/qed_dev.c diff | blob | history
drivers/net/ethernet/qlogic/qed/qed_reg_addr.h diff | blob | history
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