]> git.baikalelectronics.ru Git - uboot.git/commit
riscv: Fix context restore before returning from trap handler
authorBin Meng <bmeng.cn@gmail.com>
Wed, 12 Dec 2018 14:12:42 +0000 (06:12 -0800)
committerAndes <uboot@andestech.com>
Tue, 18 Dec 2018 01:56:27 +0000 (09:56 +0800)
commit68a1ee948dff1c5d60f89bf5d8bdb4f6e09d37d4
treec8484b9d177173fa3220163ccace7c0ecb8203c3
parentdb1cfde67333fcc011377c7afea566d11cfdd087
riscv: Fix context restore before returning from trap handler

sp cannot be loaded before restoring other registers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
arch/riscv/cpu/mtrap.S