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clk: renesas: r8a7795: Add CR clock
authorGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 17 May 2018 09:04:15 +0000 (11:04 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 19 Jun 2018 08:19:51 +0000 (10:19 +0200)
commit61feebff6689640d1d5186811055e012eadf7128
treeb552e62b9222acd545013611a84241122220d836tree | snapshot
parent0d5624e606504772b89d3c3d6b1be740ef176c61commit | diff
clk: renesas: r8a7795: Add CR clock

Add the CR core clock, which is used by the Secure Engine (SCEG).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Tested-by: Gilad Ben-Yossef <gilad@benyossef.com>
drivers/clk/renesas/r8a7795-cpg-mssr.c diff | blob | history
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