]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: Align GGTT sizes to a fence tile row
authorChris Wilson <chris@chris-wilson.co.uk>
Mon, 9 Jan 2017 16:16:09 +0000 (16:16 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 10 Jan 2017 08:12:20 +0000 (08:12 +0000)
commit5b30694b474d00f8588fa367f9562d8f2e4c7075
treebddd98d76a0ad390e2e592dce15d54db7260a64d
parent6649a0b6501d78042fd0fffaaefab1aeee27e75d
drm/i915: Align GGTT sizes to a fence tile row

Ensure the view occupies the full tile row so that reads/writes into the
VMA do not escape (via fenced detiling) into neighbouring objects - we
will pad the object with scratch pages to satisfy the fence. This
applies the lazy-tiling we employed on gen2/3 to gen4+.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170109161613.11881-2-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_tiling.c
drivers/gpu/drm/i915/i915_vma.c