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(parent: 314d894) | patch
ARM: pxa168: correct nand pmu setting
authorLei Wen <leiwen@marvell.com>
Tue, 21 Jun 2011 12:37:47 +0000 (05:37 -0700)
committerEric Miao <eric.y.miao@gmail.com>
Wed, 6 Jul 2011 15:51:36 +0000 (23:51 +0800)
commit537f601e35e188cc6f3aa26b238ed851c18fa193
tree7f534aced1211babfa537d5b1c2e5ebbc7e4566btree | snapshot
parent314d8946b0b413afdd2c26dd450805f86b353fd2commit | diff
ARM: pxa168: correct nand pmu setting

The original pair of <0x01db, 208000000> is invalid. Correct it to
the valid value.

The 6th bit of the NFC APMU register indicates NFC works whether
at 156Mhz or 78Mhz. So 0x19b indicates NFC works at 156Mhz, and
0x1db indicates it works at 78Mhz.

Signed-off-by: Lei Wen <leiwen@marvell.com>
Cc: stable@kernel.org
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
arch/arm/mach-mmp/pxa168.c diff | blob | history
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