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(parent: 86d7fe8) | patch
drm/i915: Pipe timing registers need an offset on VLV
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 24 Jan 2013 13:29:46 +0000 (15:29 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 24 Jan 2013 22:13:13 +0000 (23:13 +0100)
commit525a419efe1dae755c5f5ed10642e184d967a0d4
treee30e456d03ce4b8ad85e3ed4980b425efd7d3e62tree | snapshot
parent86d7fe8cce29bea6b6e0ba04e74d70418400a3dbcommit | diff
drm/i915: Pipe timing registers need an offset on VLV

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
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