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(parent: 714806a) | patch
gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
authorSteven Lee <steven_lee@aspeedtech.com>
Tue, 14 Dec 2021 04:02:38 +0000 (12:02 +0800)
committerBartosz Golaszewski <brgl@bgdev.pl>
Mon, 3 Jan 2022 09:50:12 +0000 (10:50 +0100)
commit4d7f57fa3371bcbdfff9a0d78f82bf1e3ab9fa1e
tree304bf0f03399622a453c459453d6734f96bacf46tree | snapshot
parent714806aa5ddb01864854ad8ab7144d3453fb1708commit | diff
gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler

Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
The hwirq base for each sgpio bank should be multiples of 64 rather than
multiples of 32.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
drivers/gpio/gpio-aspeed-sgpio.c diff | blob | history
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