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(parent: 1adecee) | patch
drm/i915: Add some L3 registers to the parser whitelist
authorBrad Volkin <bradley.d.volkin@intel.com>
Tue, 17 Jun 2014 21:10:34 +0000 (14:10 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 17 Jun 2014 22:48:35 +0000 (00:48 +0200)
commit4ca54b48d85e88f0f5890c280697d337ae17d898
treebc0e9d8d9155ac38644f461f1d8945f8a781e1eetree | snapshot
parent1adeceed2551b957a6a48b4dc1afd46c0d348dc3commit | diff
drm/i915: Add some L3 registers to the parser whitelist

Beignet needs these in order to program the L3 cache config for
OpenCL workloads, particularly when using SLM.

Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_cmd_parser.c diff | blob | history
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
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